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    <title>The Silicon Valley — Chips</title>
    <link>https://thesiliconvalley.news/category/chips</link>
    <description>Silicon, foundries, GPUs — the substrate of everything.</description>
    <language>en-us</language>
    <lastBuildDate>Fri, 24 Jul 2026 15:36:02 GMT</lastBuildDate>
    
    <item>
      <title><![CDATA[AMD and Cerebras Unveil Helios AI Rack-Scale Platform Combining EPYC CPUs and Wafer-Scale Engines]]></title>
      <link>https://thesiliconvalley.news/amd-and-cerebras-unveil-helios-ai-rack-scale-platform-combining-epyc-cpus-and-wa</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/amd-and-cerebras-unveil-helios-ai-rack-scale-platform-combining-epyc-cpus-and-wa</guid>
      <pubDate>Fri, 24 Jul 2026 11:49:11 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[AMD and Cerebras collaborate to integrate EPYC processors with Cerebras' wafer-scale AI engines in the Helios platform, targeting low-latency, high-throughput AI inference workloads for data centers.]]></description>
    </item>
    <item>
      <title><![CDATA[Nvidia Rubin architecture advances inference efficiency from GPU to rack scale]]></title>
      <link>https://thesiliconvalley.news/nvidia-rubin-architecture-advances-inference-efficiency-from-gpu-to-rack-scale</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/nvidia-rubin-architecture-advances-inference-efficiency-from-gpu-to-rack-scale</guid>
      <pubDate>Wed, 22 Jul 2026 11:55:56 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Nvidia reveals architectural enhancements in its Rubin GPU platform focused on boosting inference performance and power efficiency across the data center hierarchy.]]></description>
    </item>
    <item>
      <title><![CDATA[ZEISS Crossbeam 750 Advances Low-kV FIB Finishing for Semiconductor Failure Analysis]]></title>
      <link>https://thesiliconvalley.news/zeiss-crossbeam-750-advances-low-kv-fib-finishing-for-semiconductor-failure-anal</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/zeiss-crossbeam-750-advances-low-kv-fib-finishing-for-semiconductor-failure-anal</guid>
      <pubDate>Tue, 21 Jul 2026 11:53:47 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[The ZEISS Crossbeam 750 FIBSEM introduces uninterrupted low-kV focused ion beam milling, enhancing TEM lamella preparation and tomography with higher resolution and faster acquisition.]]></description>
    </item>
    <item>
      <title><![CDATA[AMD’s 10-Core Medusa Point APU Sets New Single-Core Performance Benchmark]]></title>
      <link>https://thesiliconvalley.news/amds-10-core-medusa-point-apu-sets-new-single-core-performance-benchmark</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/amds-10-core-medusa-point-apu-sets-new-single-core-performance-benchmark</guid>
      <pubDate>Mon, 20 Jul 2026 12:23:39 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[AMD’s upcoming 10-core Medusa Point mobile APU achieves its highest Geekbench single-core score yet, surpassing all other x86 mobile chips and signaling a major leap in mobile CPU performance.]]></description>
    </item>
    <item>
      <title><![CDATA[Nvidia RTX 50 Super GPUs delayed by prohibitive GDDR7 memory pricing]]></title>
      <link>https://thesiliconvalley.news/nvidia-rtx-50-super-gpus-delayed-by-prohibitive-gddr7-memory-pricing</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/nvidia-rtx-50-super-gpus-delayed-by-prohibitive-gddr7-memory-pricing</guid>
      <pubDate>Sun, 19 Jul 2026 11:16:48 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Nvidia's next-gen RTX 50 Super GPUs face launch delays as the cost of 3GB GDDR7 memory modules triples that of 2GB variants, threatening to push prices well beyond targets.]]></description>
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    <item>
      <title><![CDATA[ASML’s Low-NA EUV Price Hike Threatens TSMC’s Expansion Plans with Multi-Billion Cost Impact]]></title>
      <link>https://thesiliconvalley.news/asmls-low-na-euv-price-hike-threatens-tsmcs-expansion-plans-with-multi-billion-c</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/asmls-low-na-euv-price-hike-threatens-tsmcs-expansion-plans-with-multi-billion-c</guid>
      <pubDate>Sat, 18 Jul 2026 11:12:23 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[ASML’s decision to raise prices on its Low-NA EUV lithography tools challenges TSMC’s capital expenditure strategy, potentially reshaping foundry capacity growth and semiconductor node progression.]]></description>
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    <item>
      <title><![CDATA[TSMC's A14 Process Advances Yield and Performance, Attracting AI and Smartphone Demand]]></title>
      <link>https://thesiliconvalley.news/tsmcs-a14-process-advances-yield-and-performance-attracting-ai-and-smartphone-de</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/tsmcs-a14-process-advances-yield-and-performance-attracting-ai-and-smartphone-de</guid>
      <pubDate>Fri, 17 Jul 2026 21:03:25 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[TSMC reports that its A14 process technology is progressing ahead of N2, delivering notable yield and performance gains, drawing strong interest from AI, HPC, and smartphone sectors.]]></description>
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    <item>
      <title><![CDATA[Intel pioneers high-volume logic chips with ASML's High-NA EUV on 18A Panther Lake]]></title>
      <link>https://thesiliconvalley.news/intel-pioneers-high-volume-logic-chips-with-asmls-high-na-euv-on-18a-panther-lak</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intel-pioneers-high-volume-logic-chips-with-asmls-high-na-euv-on-18a-panther-lak</guid>
      <pubDate>Thu, 16 Jul 2026 11:47:42 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel has become the first to deploy ASML’s High Numerical Aperture EUV lithography in high-volume production for select layers of its 18A Panther Lake processors, marking a key step in advanced node manufacturing.]]></description>
    </item>
    <item>
      <title><![CDATA[Intel commits $5.7B to Ireland fab to meet HPC demand after German project cancellation]]></title>
      <link>https://thesiliconvalley.news/intel-commits-57b-to-ireland-fab-to-meet-hpc-demand-after-german-project-cancell</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intel-commits-57b-to-ireland-fab-to-meet-hpc-demand-after-german-project-cancell</guid>
      <pubDate>Wed, 15 Jul 2026 11:42:41 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel's $5.7 billion investment in a new fab in Ireland leverages its proven Fab 34 pipeline and Intel 3 node to address growing HPC market needs, marking a strategic pivot from its cancelled German and Polish projects.]]></description>
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    <item>
      <title><![CDATA[Intel launches Starfire, a space-grade Panther Lake SoC with Intel 3 GPU for US government]]></title>
      <link>https://thesiliconvalley.news/intel-launches-starfire-a-space-grade-panther-lake-soc-with-intel-3-gpu-for-us-g</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intel-launches-starfire-a-space-grade-panther-lake-soc-with-intel-3-gpu-for-us-g</guid>
      <pubDate>Tue, 14 Jul 2026 11:39:00 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel's new Starfire system-on-chip integrates an 18A CPU and advanced GPU on Intel 3 node, targeting space applications for US government use.]]></description>
    </item>
    <item>
      <title><![CDATA[Apple's M7 Ultra Chip Targets 1.5TB Unified Memory and Blackwell-Class AI Performance]]></title>
      <link>https://thesiliconvalley.news/apples-m7-ultra-chip-targets-15tb-unified-memory-and-blackwell-class-ai-performa</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/apples-m7-ultra-chip-targets-15tb-unified-memory-and-blackwell-class-ai-performa</guid>
      <pubDate>Mon, 13 Jul 2026 12:37:25 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Apple is designing the M7 Ultra chip to support up to 1.5TB of unified memory and AI performance rivaling Nvidia's Blackwell accelerators, signaling a major leap in SoC capabilities contingent on easing memory constraints.]]></description>
    </item>
    <item>
      <title><![CDATA[Colibrì's novel AI model runs frontier-scale 1.5-TB on just 25GB RAM, enabling local AI]]></title>
      <link>https://thesiliconvalley.news/colibris-novel-ai-model-runs-frontier-scale-15-tb-on-just-25gb-ram-enabling-loca</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/colibris-novel-ai-model-runs-frontier-scale-15-tb-on-just-25gb-ram-enabling-loca</guid>
      <pubDate>Sun, 12 Jul 2026 11:18:24 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Colibrì’s proof-of-concept demonstrates a breakthrough in running a 1.5-TB AI model on minimal hardware, requiring only 25GB RAM and modest CPUs, promising accessible local AI deployments.]]></description>
    </item>
    <item>
      <title><![CDATA[Rapidus Targets Competitive 2nm Wafer Pricing Below TSMC for 2027 Launch]]></title>
      <link>https://thesiliconvalley.news/rapidus-targets-competitive-2nm-wafer-pricing-below-tsmc-for-2027-launch</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/rapidus-targets-competitive-2nm-wafer-pricing-below-tsmc-for-2027-launch</guid>
      <pubDate>Sat, 11 Jul 2026 11:14:03 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Japanese chipmaker Rapidus aims to disrupt the advanced foundry market with 2nm-class silicon priced around $20,000 per wafer, undercutting TSMC's rates and challenging established pricing norms.]]></description>
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      <title><![CDATA[Sideways Chip Stacking Emerges as Key to Scaling AI Memory Amid Thermal Challenges]]></title>
      <link>https://thesiliconvalley.news/sideways-chip-stacking-emerges-as-key-to-scaling-ai-memory-amid-thermal-challeng</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/sideways-chip-stacking-emerges-as-key-to-scaling-ai-memory-amid-thermal-challeng</guid>
      <pubDate>Thu, 09 Jul 2026 12:45:01 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[As AI workloads demand ever-larger memory capacity and bandwidth, chipmakers explore lateral stacking of DRAM dies to overcome thermal limits and boost high-bandwidth memory density.]]></description>
    </item>
    <item>
      <title><![CDATA[Intel to Reintroduce AVX-512 in Nova Lake CPUs, Enabling Native 512-bit Execution on P-cores and E-cores]]></title>
      <link>https://thesiliconvalley.news/intel-to-reintroduce-avx-512-in-nova-lake-cpus-enabling-native-512-bit-execution</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intel-to-reintroduce-avx-512-in-nova-lake-cpus-enabling-native-512-bit-execution</guid>
      <pubDate>Wed, 08 Jul 2026 11:52:25 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel's upcoming Nova Lake desktop processors will restore AVX-512 support, extending native 512-bit SIMD execution to both performance and efficiency cores, reversing the previous AVX-512 disablement and impacting AI, HPC, and multimedia workloads.]]></description>
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      <title><![CDATA[Intel's XBM Memory Architecture Proposes Backend-Transistor DRAM with UCIe for AI Workloads]]></title>
      <link>https://thesiliconvalley.news/intels-xbm-memory-architecture-proposes-backend-transistor-dram-with-ucie-for-ai</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intels-xbm-memory-architecture-proposes-backend-transistor-dram-with-ucie-for-ai</guid>
      <pubDate>Tue, 07 Jul 2026 12:33:46 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel's new XBM patent introduces a backend-transistor DRAM stack linked via UCIe chiplet interfaces, eliminating costly silicon interposers and integrating repair logic to address AI memory bottlenecks with reduced packaging complexity and cost.]]></description>
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      <title><![CDATA[Huawei Targets South Korean AI Chip Market with High-Density Atlas SuperPods]]></title>
      <link>https://thesiliconvalley.news/huawei-targets-south-korean-ai-chip-market-with-high-density-atlas-superpods</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/huawei-targets-south-korean-ai-chip-market-with-high-density-atlas-superpods</guid>
      <pubDate>Mon, 06 Jul 2026 13:57:04 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Huawei plans to challenge Nvidia in South Korea by deploying Atlas SuperPods with 8,192 Ascend 950 AI accelerators, promising triple inference performance at a quarter of the cost.]]></description>
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      <title><![CDATA[South Korean Giants Commit $550B to Expand Memory Fab Capacity Amid AI Demand Surge]]></title>
      <link>https://thesiliconvalley.news/south-korean-giants-commit-550b-to-expand-memory-fab-capacity-amid-ai-demand-sur</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/south-korean-giants-commit-550b-to-expand-memory-fab-capacity-amid-ai-demand-sur</guid>
      <pubDate>Sun, 05 Jul 2026 21:10:50 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[South Korea’s top memory manufacturers are investing over $550 billion to build new DRAM and NAND fabs, aiming to alleviate global supply constraints and support AI-driven computing growth.]]></description>
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      <title><![CDATA[Intel Resolves Wafer-to-Wafer Yield Issues on 18A Process, Boosting Production Capacity]]></title>
      <link>https://thesiliconvalley.news/intel-resolves-wafer-to-wafer-yield-issues-on-18a-process-boosting-production-ca</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intel-resolves-wafer-to-wafer-yield-issues-on-18a-process-boosting-production-ca</guid>
      <pubDate>Fri, 03 Jul 2026 12:15:55 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel has reportedly fixed critical wafer-to-wafer yield problems on its 18A node, enabling production ramp to 15,000 wafers monthly across two sites, a key step for its next-gen process viability.]]></description>
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      <title><![CDATA[Valar Atomics Demonstrates Nuclear Microreactor Powering Nvidia RTX Spark, Plans 30MW AI Data Center]]></title>
      <link>https://thesiliconvalley.news/valar-atomics-demonstrates-nuclear-microreactor-powering-nvidia-rtx-spark-plans-</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/valar-atomics-demonstrates-nuclear-microreactor-powering-nvidia-rtx-spark-plans-</guid>
      <pubDate>Thu, 02 Jul 2026 12:17:06 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Valar Atomics successfully powered an Nvidia RTX Spark desktop PC using its Ward 250 nuclear microreactor, marking a first in live nuclear microreactor demonstration. The startup plans a 30MW closed-loop AI data center with Nvidia, eliminating local water use.]]></description>
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      <title><![CDATA[AMD Confirms Low-Power CPU Cores for Zen 6, Signaling Shift to Heterogeneous Architectures]]></title>
      <link>https://thesiliconvalley.news/amd-confirms-low-power-cpu-cores-for-zen-6-signaling-shift-to-heterogeneous-arch</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/amd-confirms-low-power-cpu-cores-for-zen-6-signaling-shift-to-heterogeneous-arch</guid>
      <pubDate>Wed, 01 Jul 2026 12:40:52 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[AMD’s Linux kernel patch reveals integration of low-power cores in upcoming Zen 6 CPUs, adopting a hybrid architecture akin to Intel’s Alder Lake, targeting improved energy efficiency for background tasks.]]></description>
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      <title><![CDATA[Imec's roadmap redefines Moore's Law with 0.3nm nodes and CFET by 2038]]></title>
      <link>https://thesiliconvalley.news/imecs-roadmap-redefines-moores-law-with-03nm-nodes-and-cfet-by-2038</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/imecs-roadmap-redefines-moores-law-with-03nm-nodes-and-cfet-by-2038</guid>
      <pubDate>Mon, 29 Jun 2026 14:14:30 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Imec projects 0.3nm process nodes by 2038 and viable CFET transistors at 0.7nm, shifting focus from CPP scaling to cell size for transistor density gains.]]></description>
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      <title><![CDATA[Intel's 52-Core Nova Lake CPU Hits 474W, Demands Triple 8-Pin Power on LGA1954 Boards]]></title>
      <link>https://thesiliconvalley.news/intels-52-core-nova-lake-cpu-hits-474w-demands-triple-8-pin-power-on-lga1954-boa</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intels-52-core-nova-lake-cpu-hits-474w-demands-triple-8-pin-power-on-lga1954-boa</guid>
      <pubDate>Sun, 28 Jun 2026 11:53:50 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel's upcoming 52-core Nova Lake processor ramps power consumption to 474W PL2, pushing motherboard design with triple 8-pin EPS connectors on the new LGA1954 platform.]]></description>
    </item>
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      <title><![CDATA[3D Hybrid Bonding Advances Push Chip Stacking Toward Atomic-Scale Integration]]></title>
      <link>https://thesiliconvalley.news/3d-hybrid-bonding-advances-push-chip-stacking-toward-atomic-scale-integration</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/3d-hybrid-bonding-advances-push-chip-stacking-toward-atomic-scale-integration</guid>
      <pubDate>Sat, 27 Jun 2026 11:42:36 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Hybrid bonding in 3D chip stacking is breaking records, enabling denser, more efficient semiconductor integration as transistor scaling nears atomic limits.]]></description>
    </item>
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      <title><![CDATA[IBM Develops 0.7nm-Class Process with Nanostack Transistors for Major Efficiency Gains]]></title>
      <link>https://thesiliconvalley.news/ibm-develops-07nm-class-process-with-nanostack-transistors-for-major-efficiency-</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/ibm-develops-07nm-class-process-with-nanostack-transistors-for-major-efficiency-</guid>
      <pubDate>Fri, 26 Jun 2026 12:20:41 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[IBM's breakthrough 0.7nm-class node leverages nanostack transistor architecture, doubling FEOL steps to achieve up to 50% performance uplift and 70% energy efficiency improvement over its 2nm-class technology.]]></description>
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      <title><![CDATA[Broadcom and OpenAI Launch Jalapeño: A New Custom Inference ASIC]]></title>
      <link>https://thesiliconvalley.news/broadcom-and-openai-launch-jalapeno-a-new-custom-inference-asic</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/broadcom-and-openai-launch-jalapeno-a-new-custom-inference-asic</guid>
      <pubDate>Thu, 25 Jun 2026 12:30:02 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[OpenAI and Broadcom have introduced Jalapeño, a custom-designed inference ASIC, signaling a strategic shift towards purpose-built silicon for AI workloads. This collaboration highlights a rapid nine-month development cycle and emphasizes performance-per-watt optimization.]]></description>
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      <title><![CDATA[Legacy Nvidia Silicon Prices Triple in China Amid Smuggling Crackdown]]></title>
      <link>https://thesiliconvalley.news/legacy-nvidia-silicon-prices-triple-in-china-amid-smuggling-crackdown</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/legacy-nvidia-silicon-prices-triple-in-china-amid-smuggling-crackdown</guid>
      <pubDate>Wed, 24 Jun 2026 12:28:30 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A tightening customs freeze on smuggled AI hardware has sent the black market price of five-year-old Nvidia A100 servers soaring to $82,000, underscoring the extreme premium on CUDA compatibility.]]></description>
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      <title><![CDATA[Qualcomm Bets on Ultra-Low-Power Silicon for Post-Smartphone AI Wearables]]></title>
      <link>https://thesiliconvalley.news/qualcomm-bets-on-ultra-low-power-silicon-for-post-smartphone-ai-wearables</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/qualcomm-bets-on-ultra-low-power-silicon-for-post-smartphone-ai-wearables</guid>
      <pubDate>Mon, 22 Jun 2026 15:29:51 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Qualcomm is diversifying its silicon portfolio with two new platforms targeting AI-driven wearables, signaling a shift toward ultra-low-power edge computing.]]></description>
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      <title><![CDATA[Tensordyne Bets on Logarithmic Number Systems to Slash AI Compute Power]]></title>
      <link>https://thesiliconvalley.news/tensordyne-bets-on-logarithmic-number-systems-to-slash-ai-compute-power</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/tensordyne-bets-on-logarithmic-number-systems-to-slash-ai-compute-power</guid>
      <pubDate>Sun, 21 Jun 2026 12:15:48 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[By replacing power-hungry floating-point multipliers with logarithmic addition, silicon startup Tensordyne aims to challenge Nvidia's dominance in hardware efficiency.]]></description>
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      <title><![CDATA[Imec, ASML, and TSMC Demonstrate 300mm Integration of Complementary 2D Transistors]]></title>
      <link>https://thesiliconvalley.news/imec-asml-and-tsmc-demonstrate-300mm-integration-of-complementary-2d-transistors</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/imec-asml-and-tsmc-demonstrate-300mm-integration-of-complementary-2d-transistors</guid>
      <pubDate>Fri, 19 Jun 2026 13:42:01 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A collaboration between imec, ASML, and TSMC has successfully integrated n-type and p-type 2D-material transistors at a 50nm pitch on 300mm wafers, marking a major milestone for post-silicon sub-1nm scaling.]]></description>
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      <title><![CDATA[Trump's Apple-Intel Chip Claim Sparks Foundry Market Speculation]]></title>
      <link>https://thesiliconvalley.news/trumps-apple-intel-chip-claim-sparks-foundry-market-speculation</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/trumps-apple-intel-chip-claim-sparks-foundry-market-speculation</guid>
      <pubDate>Thu, 18 Jun 2026 13:38:15 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A presidential assertion about an Apple-Intel chip collaboration, though unconfirmed, highlights potential shifts in US semiconductor manufacturing and supply chain strategies.]]></description>
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      <title><![CDATA[Intel's 18A-P Process Enters Risk Production, Enhancing Foundry Offerings]]></title>
      <link>https://thesiliconvalley.news/intels-18a-p-process-enters-risk-production-enhancing-foundry-offerings</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intels-18a-p-process-enters-risk-production-enhancing-foundry-offerings</guid>
      <pubDate>Wed, 17 Jun 2026 13:52:21 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel's enhanced 18A-P process has entered risk production, marking a significant step in its foundry roadmap by offering a 9% performance uplift at iso-power and 40% thermal resistance reduction. This 'drop-in' upgrade provides a compelling option for future silicon designs.]]></description>
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      <title><![CDATA[SMIC 7nm Teardown Reveals Tight Metal Pitch but Deep Density Deficit]]></title>
      <link>https://thesiliconvalley.news/smic-7nm-teardown-reveals-tight-metal-pitch-but-deep-density-deficit</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/smic-7nm-teardown-reveals-tight-metal-pitch-but-deep-density-deficit</guid>
      <pubDate>Tue, 16 Jun 2026 15:20:23 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A physical teardown of Huawei's Kirin 9030 SoC reveals that SMIC's third-generation 7nm process achieves a 32.5nm metal pitch, but lacks the architectural scaling of Western nodes.]]></description>
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      <title><![CDATA[Intel Revives Raptor Lake Architecture Again to Anchor Budget Core 200 Lineup]]></title>
      <link>https://thesiliconvalley.news/intel-revives-raptor-lake-architecture-again-to-anchor-budget-core-200-lineup</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/intel-revives-raptor-lake-architecture-again-to-anchor-budget-core-200-lineup</guid>
      <pubDate>Mon, 15 Jun 2026 15:54:43 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[Intel is reportedly planning a second refresh of its Raptor Lake architecture under the Core 200 branding, leveraging mature silicon to fill budget tiers alongside next-generation Nova Lake processors.]]></description>
    </item>
    <item>
      <title><![CDATA[AMD Debuts $3,999 Ryzen AI Halo Dev Kit to Challenge Nvidia DGX Spark]]></title>
      <link>https://thesiliconvalley.news/amd-debuts-3999-ryzen-ai-halo-dev-kit-to-challenge-nvidia-dgx-spark</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/amd-debuts-3999-ryzen-ai-halo-dev-kit-to-challenge-nvidia-dgx-spark</guid>
      <pubDate>Sun, 14 Jun 2026 12:06:39 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[AMD is targeting local AI development with a $3,999 Strix Halo-powered system, leveraging 128GB of unified memory to challenge Nvidia's workstation dominance.]]></description>
    </item>
    <item>
      <title><![CDATA[Nvidia Pivots to Arm-Based Vera CPUs in China Amid GPU Export Freezes]]></title>
      <link>https://thesiliconvalley.news/nvidia-pivots-to-arm-based-vera-cpus-in-china-amid-gpu-export-freezes</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/nvidia-pivots-to-arm-based-vera-cpus-in-china-amid-gpu-export-freezes</guid>
      <pubDate>Sat, 13 Jun 2026 11:59:25 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[With high-end GPU shipments to China blocked by US export controls, Nvidia is offering its Arm-based Vera server processors to Chinese data centers to maintain platform lock-in.]]></description>
    </item>
    <item>
      <title><![CDATA[U.S. ITC Ruling Threatens TSMC Imports Amid UMC Patent Challenge]]></title>
      <link>https://thesiliconvalley.news/us-itc-ruling-threatens-tsmc-imports-amid-umc-patent-challenge</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/us-itc-ruling-threatens-tsmc-imports-amid-umc-patent-challenge</guid>
      <pubDate>Fri, 12 Jun 2026 13:36:42 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A pending U.S. International Trade Commission ruling could block imports of specific TSMC-manufactured chips, stemming from a patent infringement claim by rival UMC. This development, backed by U.S. lawmakers, raises significant concerns for global semiconductor supply chains and]]></description>
    </item>
    <item>
      <title><![CDATA[European Satnav Startup Highlights the Complexity of Sovereign Chip Supply Chains]]></title>
      <link>https://thesiliconvalley.news/european-satnav-startup-highlights-the-complexity-of-sovereign-chip-supply-chain</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/european-satnav-startup-highlights-the-complexity-of-sovereign-chip-supply-chain</guid>
      <pubDate>Thu, 11 Jun 2026 14:07:16 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A Dutch startup's reliance on GlobalFoundries' Dresden fab for its 'all-European' silicon highlights the geopolitical and corporate compromises of regional semiconductor sovereignty.]]></description>
    </item>
    <item>
      <title><![CDATA[TSMC Scales N2 Node and Advanced Packaging for AI Era Demands]]></title>
      <link>https://thesiliconvalley.news/tsmc-scales-n2-node-and-advanced-packaging-for-ai-era-demands</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/tsmc-scales-n2-node-and-advanced-packaging-for-ai-era-demands</guid>
      <pubDate>Wed, 10 Jun 2026 13:41:45 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[TSMC's extensive fab expansion, encompassing multi-fab N2 ramps and significant CoWoS/SoIC capacity growth, directly addresses critical bottlenecks to meet escalating demand for advanced AI accelerators.]]></description>
    </item>
    <item>
      <title><![CDATA[Chinese Startup Claims DUV-Free Photonic Chip Production via Nanoimprint]]></title>
      <link>https://thesiliconvalley.news/chinese-startup-claims-duv-free-photonic-chip-production-via-nanoimprint</link>
      <guid isPermaLink="true">https://thesiliconvalley.news/chinese-startup-claims-duv-free-photonic-chip-production-via-nanoimprint</guid>
      <pubDate>Tue, 09 Jun 2026 12:48:36 GMT</pubDate>
      <category>Chips</category>
      <description><![CDATA[A Chinese startup reports successful 8-inch photonic chip wafer production using nanoimprint lithography, potentially bypassing DUV restrictions and drastically cutting manufacturing costs by 90%.]]></description>
    </item>
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