Imec's roadmap redefines Moore's Law with 0.3nm nodes and CFET by 2038

Imec’s 2026 semiconductor roadmap outlines a long-term vision that extends transistor scaling down to 0.3nm by 2038, pushing beyond the physical limits of current contact poly pitch (CPP) scaling approaches. The company highlights that traditional scaling metrics are losing relevance as CPP scaling stalls due to fundamental material and lithographic constraints.

To overcome these barriers, Imec emphasizes the transition to complementary FET (CFET) architectures, which stack transistors vertically to increase device density without shrinking lateral dimensions. According to the roadmap, CFETs will become viable around the 0.7nm node, marking a critical inflection point where three-dimensional transistor integration supersedes planar scaling.

This shift leads to a redefinition of Moore’s Law, focusing not on mere transistor pitch but on cell size and effective transistor density. The roadmap suggests that future density gains will rely more heavily on innovative transistor stacking, new materials, and advanced patterning techniques rather than incremental lithographic improvements.

For chipmakers and foundries, this roadmap signals a need to pivot R&D investments toward 3D transistor architectures and heterogeneous integration technologies. Foundries like TSMC, Samsung, and Intel will face pressure to develop manufacturing processes compatible with CFETs and sub-nanometer nodes, while EDA and design flows must adapt to new cell layouts and transistor structures.

The extended timeline to 2038 also implies that the semiconductor industry is preparing for a gradual, multi-decade transition rather than an abrupt technology leap. This offers a window for ecosystem players to innovate in materials science, process equipment, and device engineering to support these ultra-scaled nodes.