SMIC 7nm Teardown Reveals Tight Metal Pitch but Deep Density Deficit

A physical teardown of Huawei's HiSilicon Kirin 9030 system-on-chip has exposed the technical realities of China's leading semiconductor foundry, SMIC. Conducted by SemiAnalysis's new in-house teardown lab, the analysis reveals that SMIC's third-generation 7nm process (often referred to as N+3) features an incredibly aggressive minimum local metal pitch of 32.5nm. While this figure technically surpasses the metal pitch of Intel's upcoming 18A node, the physical reality of the silicon shows that SMIC remains severely disadvantaged in overall transistor density, lagging Intel's next-gen process by approximately 38 percent.

For silicon design engineers, the disparity between metal pitch and actual logic density is a masterclass in modern cell library architecture. Minimum metal pitch—the spacing between the finest metal interconnect lines—is often used as a proxy for node scaling. However, true logic density is a function of contacted poly pitch, track height, and routing efficiency. SMIC is forced to rely on deep ultraviolet (DUV) multi-patterning to print these tight metal lines, a process that dramatically increases mask counts, lowers yield, and limits routing flexibility. Without extreme ultraviolet (EUV) lithography, SMIC cannot easily reduce track heights or optimize cell layouts.

In contrast, Intel's 18A node relies on two critical architectural transitions that SMIC cannot currently replicate: RibbonFET gate-all-around transistors and PowerVia backside power delivery. PowerVia decouples the power distribution network from the signal routing layers, moving power lines to the back of the wafer. This eliminates routing congestion on the front-side metal layers, allowing Intel to achieve much higher cell library utilization and a smaller cell height. Consequently, Intel can deliver far superior logic density even with a more relaxed metal pitch, avoiding the yield-killing multi-patterning steps that SMIC must endure.

The teardown also underscores the geopolitical boundaries of foundry capacity. SMIC's ability to manufacture a 32.5nm metal pitch on DUV is a testament to the engineering resourcefulness of Chinese fabs operating under strict Western export controls. However, this approach represents an economic dead end for high-volume commercial scaling. The extreme multi-patterning required for SMIC's N+3 node drives up wafer costs and degrades throughput, making it viable only for state-subsidized national champions like Huawei rather than open-market foundry customers.

Moving forward, the industry must watch how SMIC attempts to scale beyond this third-generation 7nm platform. Without access to High-NA or even standard EUV systems, any attempt to push toward 5nm or 3nm boundaries using quadruple-patterning on DUV will face catastrophic yield curves. Meanwhile, Western foundries are standardizing backside power and gate-all-around architectures across TSMC's N2 and Intel's 18A, widening the real-world performance-per-watt gap despite what nominal metal pitch metrics might suggest.