Fujitsu Monaka Pivot: Stacking Cache on 5nm and Halving Vector Widths

At the Hot Chips 2026 symposium, Fujitsu disclosed critical architectural decisions for its upcoming 144-core Monaka server processor, scheduled for release in 2027. The Arm-based CPU represents a significant departure from the design philosophy of its predecessor, the supercomputing-focused A64FX. Instead of chasing monolithic integration, Fujitsu is embracing advanced 3D packaging by stacking the processor's entire cache on a dedicated 5nm die. This disaggregated approach allows the primary compute silicon to focus purely on execution density, signaling a broader industry shift toward specialized chiplet topologies for high-performance enterprise workloads.

The most surprising revelation from Fujitsu's presentation is the decision to narrow the chip's vector execution units. While the A64FX famously pioneered 512-bit Scalable Vector Extensions (SVE) to power the Fugaku supercomputer, Monaka will feature dual 256-bit SVE2 units per core. This modification halves the raw vector width but introduces the more versatile SVE2 instruction set. By shifting to dual 256-bit pipelines, Fujitsu aims to improve instruction throughput and energy efficiency across a wider variety of general-purpose and AI-inflected enterprise workloads, rather than optimizing solely for traditional double-precision scientific simulation.

By separating the cache from the compute cores, Fujitsu is addressing one of the most persistent bottlenecks in modern silicon manufacturing: SRAM scaling. While logic gates continue to shrink with advanced foundry nodes, SRAM cell sizes have largely stalled, consuming disproportionate die area on cutting-edge processes. Stacking the entire cache on a separate 5nm die allows Fujitsu to manufacture the core compute logic on a more advanced node while utilizing a cost-optimized, high-yield process for the memory subsystem. This 3D vertical integration ensures high-bandwidth, low-latency access to cache without ballooning the footprint of the primary compute die.

Fujitsu confirmed that Monaka will ship in two primary thermal design power (TDP) configurations: an air-cooled 350W SKU and a liquid-cooled 500W version. These power envelopes place Monaka squarely in competition with mainstream x86 and Arm server chips from AMD, Intel, and Ampere. The 500W configuration is designed to maximize the sustained clock speeds of all 144 cores under heavy multi-threaded workloads, utilizing advanced liquid cooling loops that are becoming standard in modern hyperscale data centers. Meanwhile, the 350W variant offers a drop-in option for legacy air-cooled server racks.

This architectural pivot reflects a fundamental shift in Fujitsu's market positioning. The A64FX was a bespoke, highly specialized engine designed to win benchmark crowns in high-performance computing (HPC). Monaka, by contrast, is engineered for the cloud-native and enterprise data center market. By trading the massive 512-bit vector registers for dual 256-bit units, Fujitsu is optimizing for integer math, database operations, and microservices. This brings Monaka in direct competition with Arm-based giants like Amazon's Graviton and AmpereOne, as well as AMD's Epyc line, where throughput-per-watt in virtualized environments is the dominant metric.

Looking forward, the success of Monaka will depend heavily on the maturity of Fujitsu's 3D packaging supply chain and foundry partnerships. Stacking active logic on active cache requires precise thermal management, especially given the 500W thermal ceiling of the top-tier SKU. Engineers deploying these chips in 2027 will need to evaluate whether the latency penalty of traversing the die-to-die interconnect to reach the stacked cache offsets the raw core-count advantages. If Fujitsu successfully mitigates this packaging overhead, Monaka could establish a new blueprint for how enterprise CPUs balance specialized vector execution with general-purpose throughput.