China's GAA Transistor Breakthrough Highlights Limits of Non-EUV Scaling

The recent demonstration by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) of 3nm-class gate-all-around (GAA) transistors using deep ultraviolet (DUV) lithography marks a significant, albeit narrow, technical milestone. By employing complex multi-patterning techniques to circumvent the lack of extreme ultraviolet (EUV) tools, researchers have validated the structural integration of stacked nanosheets. While this proves that the fundamental physics of GAA architectures can be realized without the industry-standard high-NA or standard EUV machinery, the transition from lab-scale wafer samples to high-volume manufacturing (HVM) remains a profound engineering divide that requires more than just transistor-level success.

The primary challenge in this non-EUV approach lies in the overlay accuracy and the cumulative error budget inherent in multi-patterning. Every additional mask layer required to define features that EUV could resolve in a single pass introduces potential defect density issues. For a 3nm-class process, where gate pitch and metal pitch are aggressively scaled, the reliance on DUV forces a reliance on immersion lithography that is increasingly prone to stochastic effects. Engineers must now contend with the reality that while they can print the features, the statistical uniformity across a 300mm wafer will likely remain insufficient for competitive yield rates compared to TSMC or Samsung.

This development forces a re-evaluation of China's domestic semiconductor roadmap, which has been severely constrained by export controls on critical lithography hardware. By mastering the GAA transistor architecture, the industry is signaling that it intends to squeeze every possible nanometer of performance out of legacy equipment. This is a strategy of attrition; if the country cannot acquire the tools to leapfrog to the latest nodes, it will attempt to compensate through sheer iterative process refinement. However, the energy and time costs associated with these multi-patterning workflows are significant, likely rendering the resulting chips less power-efficient and more expensive than those produced on EUV-native lines.

Comparing this to the current state of the global foundry sector, the gap remains stark. Leading-edge foundries are already moving toward gate-all-around nanosheets as a default requirement to manage short-channel effects at 3nm and below. By achieving this milestone, IMECAS has effectively closed the 'architectural' gap, but it has not closed the 'process integration' gap. The industry must watch how this research translates into actual logic density. A transistor that works in a test bench is fundamentally different from a library of standard cells that can be synthesized into a viable, high-performance processor architecture at scale.

What this implies for the broader competitive landscape is an increased focus on packaging and chiplet-based strategies. If monolithic scaling remains hindered by lithography limitations, we should expect to see Chinese firms lean harder into advanced packaging technologies to aggregate smaller, less dense dies into larger functional systems. This approach mitigates the need for massive, perfect dies by allowing for higher overall yields through smaller, more manageable silicon footprints. It is a pragmatic pivot that acknowledges the limitations of the current toolset while maintaining a trajectory toward high-performance computing capabilities despite the ongoing trade restrictions.

Looking forward, the critical metric to monitor is the defect density reported in subsequent pilot runs. If IMECAS can demonstrate a pathway to reduce the number of masks required for these GAA structures, it might eventually find a viable path to limited-volume production of specialized hardware. However, without access to the latest EUV scanners, the cost-per-transistor will almost certainly remain prohibitive for consumer-grade silicon. The sector is watching to see if this is a genuine breakthrough in manufacturing efficiency or merely a high-cost research demonstration that highlights the immense difficulty of competing with the global state-of-the-art without the requisite lithographic foundation.