Foundries Diverge on CFET Architectures as Transistor Stacking Limits Approach

As sub-2nm process nodes push the limits of horizontal scaling, the semiconductor industry is preparing for its most radical architectural shift since the introduction of FinFET: the Complementary Field-Effect Transistor (CFET). By stacking n-type and p-type nanosheet transistors directly on top of each other, chipmakers aim to slash cell areas by up to 50 percent. However, as the industry targets high-volume manufacturing for the end of the decade, the consensus on how to build these vertical stacks is fracturing. Leading foundries and research institutions are diverging on whether to pursue monolithic integration or sequential bonding, exposing deep disagreements over yield viability and thermal budgets.

The primary fault line in CFET development lies between monolithic fabrication and sequential 3D integration. Monolithic CFET, championed by research consortia like imec and key toolmakers, constructs both the bottom and top transistors on a single silicon substrate using a highly complex, high-aspect-ratio process flow. This approach minimizes parasitic capacitance and offers the tightest vertical interconnect density, but it introduces extreme manufacturing hurdles. Etching and filling source-drain contacts through a towering stack of alternating silicon and silicon-germanium layers requires unprecedented plasma etch selectivity and exposes the bottom device to damaging thermal cycles during top-device fabrication.

In contrast, sequential CFET—often referred to as 3D stacked or bonded CFET—takes a modular approach. Engineers fabricate the n-type and p-type devices on separate donor wafers under optimized conditions before bonding them together face-to-face or face-to-back. This decoupling allows foundries to use standard, high-performance thermal budgets for both transistors without worrying about degrading the underlying layer. However, sequential integration shifts the engineering burden from high-aspect-ratio etching to sub-nanometer wafer-to-wafer alignment. Even a minor overlay error during bonding can ruin the vertical vias connecting the gates, leading to high resistance and catastrophic yield loss.

Recent disclosures from IBM and its research partners highlight how these fabrication challenges are forcing companies to make early architectural bets. IBM, which has historically pioneered gate-all-around (GAA) nanosheet technologies at its Albany NanoTech Complex, is exploring hybrid approaches that seek to balance the thermal benefits of sequential processing with the density advantages of monolithic designs. The company's research indicates that managing the parasitic RC delay—the resistance-capacitance product that limits switching speeds—remains the critical bottleneck. As the physical distance between the stacked channels shrinks to tens of nanometers, parasitic capacitance between the top and bottom gates threatens to negate the performance gains of scaling.

Thermal management presents another massive hurdle that varies significantly between the two fabrication paths. Stacking two active transistor channels on top of each other effectively doubles the power density per unit of silicon area, creating localized hot spots that are difficult to cool. In a monolithic CFET, the bottom transistor is trapped beneath the top device and dielectric isolation layers, severely restricting its heat dissipation path to the substrate. Sequential CFET offers slightly more flexibility in incorporating specialized heat-spreading materials, such as thin-film diamond or high-conductivity dielectrics, between the bonded layers, though this further complicates the material stack and mechanical stress profiles of the wafer.

This architectural divergence will heavily influence the competitive dynamics among TSMC, Intel, and Samsung. Currently, all three foundries are transitioning to first- and second-generation nanosheet architectures, such as Intel's RibbonFET and TSMC's N2. CFET is widely slated to succeed these nodes around the 1nm or sub-1nm era, likely in the early 2030s. The choice of CFET integration method will dictate not only the capital expenditure required for new cleanroom tooling—such as advanced atomic layer deposition (ALD) and extreme ultraviolet (EUV) lithography systems—but also the physical design kits (PDKs) provided to fabless chip designers.

Looking ahead, the critical metric to monitor is the electrical performance of the vertical contact vias, particularly the contact resistance at the sub-10nm scale. Foundries must prove they can reliably deposit barrier metals and fill contact trenches without creating voids that disrupt current flow. Additionally, backside power delivery networks (BSPDN), which are just now entering production in standard nanosheet nodes, must be seamlessly integrated into CFET architectures to supply current to both stacked tiers. The coming years of pilot-line testing will determine whether monolithic or sequential processing wins the manufacturing crown, shaping the physical reality of next-generation silicon.