Foundry Roadmaps Diverge as AI Interconnects Move from Copper to Optics

The physical limits of copper interconnects are rapidly becoming the primary bottleneck in scaling AI supercomputers. As training clusters swell to tens of thousands of accelerators, the energy required to push electrical signals across copper traces over even short distances is unsustainable. This thermal and bandwidth wall is forcing a fundamental architectural shift toward silicon photonics. Rather than relying on traditional pluggable optical transceivers, the semiconductor industry is moving toward Co-Packaged Optics (CPO), which integrates optical engines directly onto the same package as the compute silicon. This transition is redefining the role of foundries, turning them into packaging integrators that must co-design silicon, optics, and substrate.

TSMC is leveraging its dominant position in advanced packaging to establish an early lead in the CPO landscape. The Taiwanese foundry's roadmap centers on its Compact Universal Photonic Engine (COUPE) technology, which stacks an optical engine directly on top of an electrical driver die using 3D hybrid bonding. By using its established Chip-on-Wafer-on-Substrate (CoWoS) platform, TSMC can integrate these COUPE tiles alongside high-bandwidth memory and main compute dies on a single interposer. This tight integration minimizes parasitic capacitance and dramatically reduces signal loss, allowing for high-density optical I/O. For system architects, TSMC's approach offers a highly integrated, low-latency path, though it locks customers tightly into its proprietary packaging ecosystem.

Intel Foundry is taking a distinct path, drawing on its decades of internal research in silicon photonics. Unlike competitors that rely on external laser sources or separate optical dies, Intel has pioneered the integration of indium phosphide lasers directly onto silicon wafers at the fab level. This integrated laser approach simplifies the physical packaging process and improves reliability by eliminating the need for complex external optical alignment. Intel plans to couple this silicon photonics capability with its Foveros 3D packaging technology, positioning itself as a vertically integrated provider that can manufacture the compute, memory interfaces, and optical engines under a single roof. This strategy appeals to designers seeking to minimize supply chain fragmentation.

Samsung Foundry is positioning itself as the flexible, open-standard alternative to TSMC and Intel. The South Korean giant is developing its own CPO solutions under its I-Cube packaging family, focusing on modularity and interoperability. Samsung's roadmap emphasizes compatibility with emerging industry standards like the Optical I/O Chiplet Consortium and Universal Chiplet Interconnect Express (UCIe). By focusing on standardized electrical interfaces between the compute die and the optical engine, Samsung aims to capture customers who want to mix and match silicon from different foundries. This approach reduces vendor lock-in but places a heavier burden on system designers to ensure signal integrity across disparate silicon blocks.

GlobalFoundries is targeting a different segment of the market by focusing on monolithic silicon photonics rather than advanced 3D stacking. Through its GF Fotonix platform, the foundry integrates RF, digital, and silicon photonics components onto a single silicon-on-insulator (SOI) wafer. While this monolithic approach is manufactured on older, more mature process nodes, it offers exceptional cost-efficiency and thermal stability for optical transceivers and near-packaged optics. GlobalFoundries is positioning itself as the ideal manufacturing partner for fabless optical engine startups that need to interface with advanced compute dies produced elsewhere, carving out a high-volume niche that bypasses the ultra-expensive packaging wars.

The divergence in these foundry roadmaps highlights a deeper industry debate over system-level trade-offs. TSMC's tightly integrated COUPE platform offers the highest performance and lowest power consumption per bit, but it demands that the entire silicon sandwich be processed within a single, highly constrained supply chain. Conversely, modular approaches from Samsung and the monolithic offerings from GlobalFoundries provide greater flexibility and lower entry costs, but they introduce physical distance between the compute logic and the optical driver, which slightly degrades latency and power efficiency. For engineers deploying next-generation clusters, the choice of foundry is no longer just about transistor density; it is about choosing a packaging and optical integration philosophy.

Looking ahead, the critical metric to monitor is the yield rate of these complex multi-die assemblies. Integrating lasers and optical waveguides onto silicon substrates introduces unique failure modes, particularly under the high thermal stress of AI workloads. If foundries cannot achieve commercial-grade yields for co-packaged optics, the industry may be forced to rely on intermediate solutions like near-packaged optics (NPO) for longer than anticipated. Furthermore, the standardization of optical interfaces will dictate how quickly CPO can democratize. The foundry that successfully balances optical performance with manufacturing yield will likely dictate the physical architecture of the next decade's AI supercomputers.