GlobalFoundries Joins TSMC CoWoS Supply Chain to Build US Interposers

In a major realignment of the advanced packaging landscape, GlobalFoundries has entered into a five-year, $2 billion agreement with TSMC to manufacture silicon interposers for Chip-on-Wafer-on-Substrate packaging. The partnership integrates GlobalFoundries into TSMC's high-performance computing supply chain within the United States. By leveraging its existing mature-node manufacturing capabilities, GlobalFoundries can participate directly in the high-volume AI accelerator market. This strategy allows the company to secure high-margin revenue without undergoing the massive capital expenditures required to develop and build sub-5nanometer logic manufacturing facilities.

Silicon interposers are the unsung foundation of modern generative AI hardware, acting as the ultra-dense routing medium that connects high-bandwidth memory stacks to the central graphics processing unit or application-specific integrated circuit. While the main compute dies require leading-edge nodes like 4nanometer or 3nanometer, the passive interposers themselves are typically fabricated using mature 65nanometer or 45nanometer lithography. GlobalFoundries will produce these large-area silicon substrates at its Fab 8 facility in Malta, New York, utilizing its established manufacturing lines to supply TSMC's domestic packaging operations.

The partnership directly addresses one of the most critical vulnerabilities in the global semiconductor supply chain: the concentration of advanced packaging in Taiwan. While TSMC has committed tens of billions of dollars to construct leading-edge logic fabs in Arizona, the lack of domestic advanced packaging facilities has threatened to send US-manufactured silicon back to Asia for final assembly. By outsourcing interposer fabrication to GlobalFoundries, TSMC can accelerate the establishment of an end-to-end advanced packaging pipeline on US soil, satisfying both commercial demands for supply chain resilience and federal requirements for domestic manufacturing.

For GlobalFoundries, this agreement is a resounding validation of its pivot away from the leading-edge node race in 2018. When the company halted its 7nanometer development to focus on specialized mature processes, critics questioned its long-term relevance in a market dominated by sub-3nanometer scaling. However, as monolithic dies reach their physical limits and chiplet architectures become the industry standard, packaging has emerged as the new scaling frontier. This deal proves that mature-node capacity remains vital to the AI revolution, as a single modern GPU package consumes several times more silicon area than its monolithic ancestors.

The economics of silicon interposers are highly favorable for mature-node foundries. Because interposers are physically large, often spanning multiple reticle limits, they consume a significant number of 300millimeter wafers while maintaining relatively high yields compared to complex logic chips. This high wafer utilization will help GlobalFoundries maintain high fab utilization rates and stable pricing. Furthermore, as the industry transitions toward larger interposer designs to accommodate eight or twelve stacks of next-generation high-bandwidth memory, the demand for precise, large-scale silicon fabrication will only intensify.

This alliance also reshapes the competitive dynamics between TSMC and Intel Foundry Services. Intel has heavily promoted its open systems foundry model, offering its proprietary EMIB and Foveros packaging technologies to external customers as a key differentiator. By partnering with GlobalFoundries, TSMC is building a decentralized but highly capable advanced packaging ecosystem in North America that directly challenges Intel's domestic packaging pitch. Tech companies looking to de-risk their supply chains now have a viable, US-based path for high-volume CoWoS assembly.

Looking forward, the success of this collaboration will depend on how seamlessly the two foundries can integrate their quality control and testing methodologies across different organizations. If successful, this partnership could expand beyond passive silicon interposers into active interposers containing embedded power management or optical interconnects. As the semiconductor industry grapples with physical scaling limits, pragmatic collaboration between nominal rivals is becoming the standard operating procedure for delivering the next generation of high-performance computing infrastructure.